This invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, this invention relates to a technology which will be useful when applied to a semiconductor integrated circuit device in which bit line conductors disposed in a memory cell region of a DRAM (Dynamic Random Access Memory) and first level interconnect conductors disposed in a peripheral circuit region of the DRAM are formed by the same layer.
Recent large capacity DRAMs employ a stacked capacitor structure in which an information storage capacitor device is disposed over a memory cell selection MISFET so as to supplement a decrease of a stored charge quantity (Cs) of the information storage capacitor device due to scaling-down of memory cells.
The information storage capacitor device of the stacked capacitor structure is formed by serially laminating a storage electrode (lower electrode), a capacity insulating film and a plate electrode (upper electrode). The storage electrode of the information storage capacitor device is connected to one of the semiconductor regions (source region and drain region) of an n-channel memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor). The plate electrode is constituted as an electrode common to a plurality of memory cells and a predetermined fixed potential (plate potential) is supplied to this plate electrode.
A bit line for writing and reading data is connected to the other of the semiconductor regions of the memory cell selection MISFET. A bit line conductor is disposed between the memory cell selection MISFET and the information storage capacitor device or over the information storage capacitor device. The structure wherein the information storage capacitor device is disposed over the bit line conductor is referred to as a "capacitor over bit line (COB)" structure.
A DRAM having the COB structure is described, for example, in U.S. Pat. No. 5,604,365 issued on Feb. 18, 1977 (corresponding to JP-A-7-122654 laid open on).
In the DRAM described in the above-mentioned reference, bit lines constituted by a polysilicon film (or a policide film) are disposed over a memory cell selection MISFET the gate electrode (word line) of which is constituted by a polysilicon film or a laminate film (policide film) of the polysilicon film and a tungsten silicide (WSix) film, and an information storage capacitor device comprising a storage electrode formed by a polysilicon film, a capacity insulating film formed by a laminate film of a silicon oxide film and a silicon nitride film and a plate electrode formed by a polysilicon film is disposed over the bit lines.
A higher integration density has been required for the DRAM having such a COB structure, too. A multi-level interconnect structure has become indispensable with the progress of scaling-down of interconnect conductors, and a three-layered interconnect structure having a minimum line width of 0.3 .mu.m has been employed in 64 Mbit DRAMs, for example.
The adoption of a multi-level interconnect technology for arranging the interconnect conductors in a multi-level configuration invites an increase in the number of process steps in the conductor formation process and eventually causes a drop of through-put of a production process. Therefore, the increase of the number of interconnect conductor levels must be reduced essentially to minimum. A proposal has been made as one of the methods of solving the problem which forms interconnect conductors of a peripheral circuit in the same process when bit lines for transferring directly memory cell information to a sense amplifier of the peripheral circuit portion are formed. In other words, a technology has been proposed which forms a part of the interconnect conductors (more specifically, a first level interconnect conductor) among the interconnect conductors of the peripheral circuit portion at the same level by the same process step as the formation step of the bit lines.
This technology is described, for example in U.S. Pat. No. 5,604,365 described above and in IEDM '94, p.635.